/* hal_dma_requests.h */
#ifndef __HAL_DMA_REQUESTS_H__
#define __HAL_DMA_REQUESTS_H__

#define DMAMUX_REQ_DISABLED       0u

#define DMAMUX_REQ_UART0_RX       2u
#define DMAMUX_REQ_UART0_TX       3u
#define DMAMUX_REQ_UART1_RX       4u
#define DMAMUX_REQ_UART1_TX       5u
#define DMAMUX_REQ_UART2_RX       6u
#define DMAMUX_REQ_UART2_TX       7u
#define DMAMUX_REQ_I2C1_RX        8u
#define DMAMUX_REQ_I2C1_TX        9u

#define DMAMUX_REQ_SPI0_RX        14u
#define DMAMUX_REQ_SPI0_TX        15u
#define DMAMUX_REQ_SPI1_RX        16u
#define DMAMUX_REQ_SPI1_TX        17u
#define DMAMUX_REQ_SPI2_RX        18u
#define DMAMUX_REQ_SPI2_TX        19u
#define DMAMUX_REQ_eTMR1_CH0      20u
#define DMAMUX_REQ_eTMR1_CH1      21u
#define DMAMUX_REQ_eTMR1_CH2      22u
#define DMAMUX_REQ_eTMR1_CH3      23u
#define DMAMUX_REQ_eTMR1_CH4      24u
#define DMAMUX_REQ_eTMR1_CH5      25u
#define DMAMUX_REQ_eTMR1_CH6      26u
#define DMAMUX_REQ_eTMR1_CH7      27u
#define DMAMUX_REQ_eTMR2_CH0      28u
#define DMAMUX_REQ_eTMR2_CH1      29u

#define DMAMUX_REQ_eTMR0          36u
#define DMAMUX_REQ_eTMR3          37u

#define DMAMUX_REQ_ADC0           42u

#define DMAMUX_REQ_I2C0_RX        44u
#define DMAMUX_REQ_I2C0_TX        45u

#define DMAMUX_REQ_ACMP0          48u
#define DMAMUX_REQ_GPIOA          49u
#define DMAMUX_REQ_GPIOB          50u
#define DMAMUX_REQ_GPIOC          51u
#define DMAMUX_REQ_GPIOD          52u
#define DMAMUX_REQ_GPIOE          53u
#define DMAMUX_REQ_FLEXCAN0       54

#define DMAMUX_REQ_ALWAYS_ON0      62u
#define DMAMUX_REQ_ALWAYS_ON1      63u

#endif /* __HAL_DMA_REQUESTS_H__ */

